Soft sphere model for electron correlation and scattering in the atomistic modelling of semiconductor devices

The atomistic modelling of silicon MOSFET devices becomes essential at deep sub-micron scales when it is no longer possible to represent the charged impurities by a continuous charge distribution with a determined doping density. Instead the spatial distribution and the actual number of dopants must be treated as discrete random variables. The present paper addresses the issue of modelling the dynamics of discrete carrier flow in a semiconductor device utilising a simple model of the carrier-carrier scattering and carrier-fixed impurity scattering which is suitable for efficient simulations of large ensembles of devices

Efficient hole transport model in warped bands for use in the simulation of Si/SiGe MOSFETs

An analytical geometric model for the valence band in strained and relaxed Si1-xGex is presented, which shows good agreement with a 6-band k·p analysis of the valence band. The geometric model allows us to define an effective mass tensor for the warped valence band structure. The model also has applications in the study of III-V semiconductors, and could aid in the interpretation of cyclotron resonance experiments in these bands. A warped three-band Monte Carlo simulation has been developed based on this model making use of the efficient calculation of trajectory dynamics that is made possible through the use of such a model. The calculated transport characteristics show good agreement with the available experimental data

Nonequilibrium hole transport in deep sub-micron well-tempered Si p-MOSFETs

Using 2D full-band MC simulations the authors study nonequilibrium transport effects and the performance potential of well tempered Si p-channel MOSFETs covering gate lengths ranging from 90nm to 25nm. By comparing MC simulations with carefully calibrated drift diffusion (DD) simulations of the same devices, they provide a quantitative estimate of the importance and the influence of nonequilibrium transport on the device performance

RF analysis methodology for Si and SiGe FETs based on transient Monte Carlo simulation

A comprehensive analysis methodology allowing investigation of the RF performance of Si and strained Si:SiGe MOSFETs is presented. It is based on transient ensemble Monte Carlo simulation which correctly describes device transport, and employs a finite element solver to account for complex device geometries. Transfer characteristics and figures of merit for a number of existing and proposed RF MOSFETs are discussed

Scaling study of Si/SiGe MODFETs for RF applications

Based on the successful calibration on a 0.25 /spl mu/m strained Si/SiGe n-type MODFET, this paper presents a gate length scaling study of double-side doped Si/SiGe MODFETs. Our simulations show that gate length scaling improves device RF performance. However, the short channel effects (SCE) along with the parasitic delays limit the device performance improvements. We find that it is necessary to consider scaling (dimensions and doping) of both the lateral and vertical architecture in order to optimize the device design

Strain engineered In_xGa_1-xAs channel pHEMTs on virtual substrates: a simulation study

The impact of In<sub>x</sub>Al<sub>1-x</sub>As strain control buffers on the performance of low In content InGaAs channel pseudomorphic high electron mobility transistor p(HEMT) is investigated. It is shown that relaxed and tensile strained channel devices outperform the conventional compressively strained channel devices. It is argued that strain engineering in GaAs based devices makes it possible to realise RF characteristics comparable to InP based pHEMTs while obtaining improved breakdown characteristics

RF performance of strained Si MODFETs and MOSFETs on "virtual" SiGe substrates: A Monte Carlo study

No abstract avaliable

Monte Carlo investigation of optimal device architectures for SiGe FETs

Strained silicon channel FETs grown on virtual SiGe substrates show clear potential for RF applications, in a material system compatible with silicon VLSI. However, the optimisation of practical RF devices requires some care. 0.1-0.12 μm gate length designs are investigated using Monte Carlo techniques. Although structures based on III-V experience show fT values of up to 94 GHz, more realistic designs are shown to be limited by parallel conduction and ill constrained effective channel lengths. Aggressively scaled SiGe devices, following state-of-the-art CMOS technologies, show fT values of up to 80 GHz

Indication of Non-equilibrium Transport in SiGe p-MOSFETs

No abstract avaliable

Enhanced velocity overshoot and transconductance in Si/Si(0.64)Ge(0.36)/Si pMOSFETs - predictions for deep submicron devices

No abstract avaliable